MPC8260 |
RFQ for MPC8260 Required Field |
 |
| Technical/Catalog Information | MPC8260ACVVMHBB |
| Vendor | Freescale Semiconductor |
| Category | Integrated Circuits (ICs) |
| Processor Type | MPC82xx PowerQUICC II 32-bit |
| Speed | 266MHz |
| Voltage | 2V |
| Features | - |
| Package / Case | 480-TBGA |
| Packaging | Tray |
| Drawing Number | 375; 1152-04; VV; 480 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | MPC8260ACVVMHBB MPC8260ACVVMHBB |
| Product | Manufacturers | Pack | D/C |
| MPC8260 | - | BGA | - |
Features |
| The major features of the MPC8260 are as follows:• Dual-issue integer core- A core version of the EC603e microprocessor- System core microprocessor supporting frequencies of 133200 MHz- Separate 16-Kbyte data and instruction caches: Four-way set associative Physically addressed LRU replacement algorithm- PowerPC architecture-compliant memory management unit (MMU)- Common on-chip processor (COP) test interface- High-performance (4.45.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz)- Supports bus snooping for data cache coherency- Floating-point unit (FPU)• Separate power supply for internal logic and for I/O• Separate PLLs for G2 core and for the CPM- G2 core and CPM can run at different frequencies for power/performance optimization- Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios• 64-bit data and 32-bit address 60x bus- Bus supports multiple master designs- Supports single- and four-beat burst transfers- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller- Supports data parity or ECC and address parity• 32-bit data and 18-bit address local bus- Single-master bus, supports external slaves- Eight-beat burst transfers- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller• System interface unit (SIU)- Clock synthesizer- Reset controller- Real-time clock (RTC) register- Periodic interrupt timer- Hardware bus monitor and software watchdog timer- IEEE 1149.1 JTAG test access port• Twelve-bank memory controller- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals- Byte wr |
| Rating |
Symbol |
Value |
Unit |
| Core supply voltage2 |
VDD |
-0.3 2.5 |
V |
| PLL supply voltage2 |
VCCSYN |
-0.3 2.5 |
V |
| I/O supply voltage3 |
VDDH |
-0.3 4.0 |
V |
| Input voltage4 |
VIN |
GND(-0.3) 3.6 |
V |
| Junction temperature |
Tj |
120 |
°C |
| Storage temperature range |
TSTG |
(-55) (+150) |
°C |
